FinFET technology is an emerging technology which provides solutions to MOSFET scaling problems at, and below, the 45 nm node. A fin field effect transistor (finFET) is a metal-oxide-semiconductor field effect transistor (MOSFET) formed on a semiconductor fin. A finFET comprises at least one narrow (preferably <10 nm wide) semiconductor fin gated on at least two opposing sides of each of the at least one semiconductor fin. FinFET structures are preferably formed on a semiconductor-on-insulator (SOI) substrate, because of the precise control of fin height which is determined by the substrate silicon thickness and ease of electrical isolation by shallow trench isolation structures.
A gate electrode is placed on at least two sides of a channel or is wrapped around the channel of the finFET. A gate dielectric separates the gate electrode and the channel of the finFET. A double gate finFET employs a double gate configuration in which the gate electrode is placed on two opposite sides of the channel. In a triple gate finFET, the gate electrode is placed on one more side of a typically rectangular channel of the transistor. In a quadruple gate finFET or a wrapped gate finFET, the gate electrode is placed on four sides of the channel.
In a typical finFET structure, at least one conducting channel on a vertical sidewall is provided within the semiconductor “fin” that is set sideways, or edgewise, upon a substrate. Typically, the fin comprises a single crystalline semiconductor material with a substantially rectangular cross-sectional area. Also typically, the height of the fin is greater than width of the fin to enable higher on-current per unit of semiconductor area used for the finFET structure.
A gate electrode located on at least two sides of the channel of the transistor is a common feature of finFETs known in the art. Increased number of sides on which the gate electrode controls the channel of the finFET enhances the controllability of the channel in a finFET compared to a planar MOSFET. Improved control of the channel allows smaller device dimensions with less short channel effects as well as larger electrical current that can be switched at high speeds. A finFET device has equivalent or higher current density, and much improved short channel control than the mainstream complementary metal-oxide-semiconductor (CMOS) technology utilizing similar critical dimensions.
Another area of advancing technology which provides enhanced performance for MOSFET scaling problems is development of high-k gate dielectric materials. High gate leakage current of nitrided silicon dioxide and depletion effect of polysilicon gate electrodes limits the performance of conventional silicon oxide based gate electrodes. High performance devices for an equivalent oxide thickness (EOT) less than 1 nm require high-k gate dielectric materials and metal gate electrodes to limit the gate leakage current and provide high on-currents. The high-k gate dielectric materials refer to dielectric metal oxides or dielectric metal silicates having a dielectric constant that is greater than the dielectric constant of silicon oxide of 3.9.
In general, complementary metal oxide semiconductor (CMOS) integration requires two gate materials, one having a work function near the valence band edge of the semiconductor material in the channel and the other having a work function near the conduction band edge of the same semiconductor material. In CMOS devices having a silicon channel, a conductive material having a work function of about 4.0 eV is necessary for n-type metal oxide semiconductor field effect transistors (NMOSFETs) and another conductive material having a work function of about 5.0 eV is necessary for p-type metal oxide semiconductor field effect transistors (PMOSFETs). In conventional CMOS devices employing polysilicon gate materials, a heavily p-doped polysilicon gate and a heavily n-doped polysilicon gate are employed to address these needs. In CMOS devices employing high-k gate dielectric materials, two metal gate materials satisfying the work function requirements are typically employed.
Thus, integration of high-k gate dielectric materials into finFET devices faces unique challenges. One of the challenges is the complexity and a large number of processing steps needed to form gate electrodes comprising a high-k gate dielectric material and dual metal gates.
In view of the above, there exists a need to provide a semiconductor structure comprising complementary finFET devices having a high-k gate dielectric material and dual metal gates and requiring a relatively small number of processing steps for manufacturing.
Another challenge in the integration of the high-k gate dielectric materials into finFET devices is an increase in parasitic capacitance between a gate wiring and adjacent conductive structures due to the high-k gate dielectric material. The high-k dielectric material, while advantageously providing a low EOT and enabling scaling of gate dielectric, is also known to act as a significant oxygen diffusion path from the isolation to the FET channel, often resulting in interfacial silicon oxide growth in the FET gate dielectric—resulting in increased EOT and thus diminishing the effectiveness of the high-k gate dielectric. Specifically, the high-k gate dielectric material is needed only on the gate electrode for scaling down of the gate dielectric, but is not desired outside the gate electrode including the gate wiring due to this interfacial oxide growth that occurs when a substantial amount of the high-k dielectric is retained over the device isolation region. Further, a set of dual high-k gate dielectric materials is preferred to a single high-k gate dielectric material for enhanced CMOS performance, complicating the integration of high-k gate dielectric materials into finFET devices.
Therefore, there exists a need for a semiconductor structure comprising complementary finFET devices having dual high-k gate dielectric materials and dual metal gates, wherein the amount of the dual high-k gate dielectric materials is minimized on a gate wiring, and method of manufacturing the same.